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COP/JTAG Port
additional signals aiding in system debug. The pinout of this connector, which is a general
Motorola recommendation for including a COP/JTAG port in a design, is shown in
Figure 5-11 and detailed in Table 5-20.
TDO
TDI
QREQ
TCK
1
3
5
7
2
4
6
8
N.C.
TRST
V3.3
N.C.
TMS
9
10 N.C.
SRESET
HRESET
CKSTP_OUT
11
13
15
12
14
16
GND
"KEY"
GND
Figure 5-11. COP/JTAG Port Connector
Table 5-20. COP/JTAG Port Signals Description
Pin No.
1
Signal Name
TDO
Attribute
O
Description
Transmit Data Out. This the JTAG’s serial data output driven by
Falling edge of TCK.
2
3
N.C.
TDI
-
I
Not Connected.
Transmit Data In. This is the JTAG serial data input, sampled by
the PowerQUICC II on the rising edge of TCK. This line is pulled
up internally by the PowerQUICC II.
4
TRST
I
Test port Reset (L). When this signal is active (Low), it resets the
JTAG logic. This line is pull-down on the MPC8272ADS with a
1K ? resistor, to provide constant reset of the JTAG logic.
5
QREQ
O
Quiescent Request (L). When asserted (low), this line indicates
that the PowerQUICC II desires to enter low-power mode. This
signal may be required by a debug station.
6
7
V3.3
TCK
O
I
3.3V power supply bus.
Test port Clock. This clock shifts in / out data to / from the
PowerQUICC II JTAG port. Data is driven on the falling edge of
TCK and is sampled both internally and externally on it’s rising
edge.
TCK is pulled up internally by the PowerQUICC II.
8
N.C.
-
Not Connected.
MPC8272ADS User Guide
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